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To Do

Next Versions

  1. Make synthesis Makefiles and configuration script rely on the prj/Makefile definition of the project only. [0%]
    • Remove SYN_FILES and put a single file with all information instead. If possible.
    • Remove module separated synthesis of Xilinx in order to accomplish the previous item.
  2. Coherently separate FPGA generic from specific modules in the directory structure. Ease inclusion of new FPGA specific modules. Review system definitions and modules selection. [0%]
  3. Update Firmwares [66%]
    1. For start we should add some comments to all files so that they become self-explanatory and then if needed rearrange the subdirectories. [15%]
      • update file names to correspond to their function. [100%]
    2. sw/support/vnprintf.c gives compilation warnings. Is this still required? [80%]
      • I don't know exactly what should be the behavior of this memchr and if it is important. I have almost no idea about this vfnprintf.c file. This seems to have been added for compatibility with or1ksim and for removing necessity of linkage to stdlib.
      • Last update of this file was on revision 36. This is the log: sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.
      • This seemed to be only necessary for or1ksim, I'd prefer to remove it for now. Once we want or1ksim to be supported, we check that again.
      • It seems minsoc_printf still exists, possibly remove that [0%]
    3. sw/support/uart.c could be merged to sw/drivers/uart.c [70%]
      • uart under support define lower level functions. uart_putc is used by minsoc_printf, this could be possibly removed and put everything under drivers and rewrite minsoc_printf or remove.
      • cross linkage of drivers/uart.h on support library not nice, possibly remove minsoc_printf completely [0%]
  4. Include a GPIO module, because many people like to use that as a test program (blinking LED). [0%]
    1. Comments on what has to be done here.
  5. Substitute the minsoc_tc_top.v for wb_conbus or wb_conmax for either simplicity or performance (shared-bus or switch). [0%]
    1. Update minsoc.odt and .pdf chapter 2.2 Wishbone Interconnect to comply with the new interconnects.
  6. Include further memory interface controllers to be selected by the configuration system, SRAM, DDR, DDR2. [0%]
    1. The inclusion of standard memory types could help users to use Linux for example or other stuff. Though this can rapidly grow out of control due to the number of available memory types. Thus, I am uncertain about how good this is. At last, for now, memory type is not configurable.
  7. Extend system configuration to software configuration. Amount of memory and memory space (base address of modules) should be automatically updated to the software headers, orp.ld and board.h to avoid configuration errors. The same way, deactivated modules should remove the respective addresses definitions from the headers so that compilation errors arise when using non-existent modules. [0%]
    • add scripts to be run when issuing make? The scripts could parse minsoc_defines.v and patch orp.ld, board.h and so on.
    • Include all target specific files in the same directory for user update.
  8. Look for a way to allow automatically insertion of new modules to minsoc_top [0%]
    • memory address input
    • automatic wishbone connection for minsoc_top
    • automatic connection to minsoc_tc_top
    • Full switch function, according to amount of masters, i.e.:
      • 2 masters, 2 buses, 2 router: arbiter has to assign correct bus to the calling master
    • Switch issues, “minsoc_tc_top.v”:
      • modules instantiated by generate cannot be accessed through variable later on
      • maybe it can be done with parameters, macro and loop only
      • possibility of using IP-XACT or even Perlilog for that
        • hardens testbench creation and raises compatibility issues (I suppose)
  9. Support ADS' integrated uart. [100%]
  10. Substitute installation script by packets for BitBake or Paludis. Less probably, but also Gentoo Prefix could be taken into consideration. [0%]
    • check which fit best:
      • unprivileged installation
      • custom installation path
      • supported operating systems

Nice to Have

  1. Include new communication controllers and develop drivers for them: I2C and CAN have been already successfully implemented for minsoc but still have to be seamless integrated to the definition file in order to be de- or activated without harming the system. I2C, CAN and an improved Ethernet driver have also been programmed and are in the queue to join the project. [70%]

Old To Dos

Version 1.0

With version 1.0, we aim at facilitating the user and developer adoption of the system. MinSoC shall be easily installable, configurable, simulatable and synthesizable. After this is done, changes to system internals and design can be made more easily. This will hopefully leverage the development of MinSoC.

  1. Adapt firmware to new toolchain: Summary of new Toolchain changes:,OpenRISC,0,3975,0#1288611962 [100%]
    1. Remove leading underscores of assembly lables used to call external C functions [100%]
    2. Update the interrupt handlers in except.S not to use the first 130 bytes to store register information prior to interrupt handling, use memory after that instead. [100%]
  2. Be compatible with both new and old toolchain. [100%]
    • Use compiler definition for adding or not the leading underscore on assembler functions. [100%]
  3. Review Makefiles for delivered firmware. [100%]
  4. Create an instantiation of a generic Altera PLL for the clock adaptation module. [100%]
    • test on some platforms [10%]
  5. Work out the Makefile System. [100%]
  6. Produce working Installation Scripts. [100%]
    • test on more platforms [30%]

Create branche for release-1.0:

  1. Roll back to or1200_v1
  2. Apply Nathan's or1200_v1 patch for watchpoints.
  3. Adapt or1200_defines.v and configure scripts under spartan3e boards of backend to be compatible with version 1 of processor.
  4. Update external subversion repositories to fixed version.
  5. Test installation/configuration scripts.
    1. OpenCores ftp not working yet.
    2. Nathan's patch need review, waiting for revision and then fix svn external link to next revision.
  6. Test synthesis, simulation with project system
    • Simulation
    • Altera Synthesis
      • No Errors
      • Working on FPGA
        1. altera_3c25_board → no errors
    • Xilinx Synthesis
      • No Errors
      • Working on FPGA
        1. spartan3a_dsp_kit
        2. spartan3e_starter_kit → no errors
        3. spartan3e_starter_kit_eth → ERRORS
          1. ethmac_defines.v xilinx memories, with area optimization and high effort, 110% (maybe without UART)
          2. without UART, Speed optimization normal effort 106%, with Area optimization on high effort: 106%
          3. standard support for spartan3e_starter_kit_eth will be dropped, every user can try to tweak as they can
  7. Adapt installation script to retrieve MinSoC from tags/release-1.0 instead of trunk.
  8. Create tags/release-1.0
  9. Copy/adapt development wiki section to release-1.0 section
pm/to_do.txt · Last modified: 2012/01/21 13:58 by Raul Fajardo