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Development: Manual Synthesis

How To

This section guides you in adapting MinSoC to synthesize it with your FPGA's vendor tool. In the linked pages of the text, some files are said to be located under various directories. You have to edit the files under minsoc/backend instead. The only exception is or1200_defines.v, but you can as well ignore the configuration of this file.

  1. Configure minsoc/backend/minsoc_defines.v. 1)
    1. Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it. In case your FPGA is neither Altera nor Xilinx, simply select GENERIC_FPGA.
    2. `define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by 4⋅2MEMORYADRWIDTH bytes, since its data width is 32 bits, the amount in Bytes is 4 times its depth. 2)
    3. Choose a clock division for your global clock related to your design max speed by changing the definition: “`define CLOCK_DIVISOR 5”. 3)
    4. Define your RESET polarity: uncomment “`define POSITIVE_RESET” for an active high reset or “`define NEGATIVE_RESET” for an active low reset and comment the other.
  2. Define user constrains for system pinout. To do so, edit or create minsoc/backend/your_board.ucf file. Here you find some examples of ucf files. More examples are found under minsoc/backend/someboard/someboard.ucf.
    • The constraint file is required to define which FPGA pins are connected to which design ports. You will have to check the user manual for your board. It will tell you which FPGA pins are connected to which board components. Then, change the FPGA pin names inside quotes after <LOC = > for every design port according to the user manual information of your board.
  3. Create project in your vendor tool, e.g. project manager (ISE, Quartus), include all Verilog files under “minsoc/rtl/verilog” and subdirectories.
  4. Include all files under “minsoc/backend”. Do not include its subdirectories or files from its subdirectories.
  5. Include the user constraint for system pinout (created on step 2) to your project on the project manager.
  6. Synthesize, P&R and upload bitfile. 4)

Only after the bitfile has been successfully uploaded, OpenRISC firmware can be uploaded and debugged, how to.

1) This link shows recommended values for different devices
2) This is not allowed to be less than 12, 11 is the memory block address width. If you change it from 13, check FAQ: How to adapt the firmware to my implementation?.
3) If your FPGA is not Altera nor Xilinx, please use only even numbers for the division. Odd numbers are going to be rounded down. If your resulting clock is not 25MHz, check FAQ: How to adapt the firmware to my implementation?.
4) If your device is full check this link for optimizations.
dev/synthesizing_manually.txt · Last modified: 2012/06/27 12:51 by Raul Fajardo