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dev:synthesis

Development: Synthesis

How To

Before synthesizing MinSoC, you have to configure your specific board.

  1. MinSoC uses a Makefile system to synthesize it's design. The system is found under minsoc/syn. If your FPGA is Altera or Xilinx, you can create the bitfile required to configure your FPGA by calling “make all” under minsoc/syn.
    /minsoc/syn$ make all
  2. After the bitfile has been generated, upload the bitfile to the FPGA using the vendor tool for this purpose.
  3. Only after the bitfile has been successfully uploaded, OpenRISC firmware can be uploaded and debugged, how to.

Windows

If you are using Windows, you can synthesize your system by clicking twice on minsoc/syn/setup.bat. You still need to configure your specific board before.

Makefile System

The system works with Altera Quartus and Xilinx ISE systems. The configuration of the system as Altera or Xilinx is made by the configure script ran under backend/your_board. Depending if Altera or Xilinx, there are the following make targets. You can always request this information by simply typing make. The make target differences lie in the different workflows taken by the different manufacturers.

  1. Altera:
    ~/or1k/minsoc/syn$ make
      all: Synthesize and implement the SoC, then generate a bit stream
    
      bitgen: Generate a programming file for the target FPGA
      map: Express the SoC netlist in the target hardware
      fit: Place the target hardware, then route the wires
      sta: Perfom a timming analysis
      eda: Generate a netlist of the hardware
      config: Load the bitstream into the device using ALTERA USB Blaster and JTAG configuration
    
      clean: Delete all superfluous files generated by Altera tools
      distclean: Delete all generated files
  2. Xilinx:
    ~/or1k/minsoc/syn$ make
      all: Synthesize and implement the SoC, then generate a bit stream
    
      soc: Synthesize the SoC
      translate: Convert the SoC's ngc file to an ngd file for mapping
      map: Express the SoC netlist in the target hardware
      par: Place the target hardware, then route the wires
      bitgen: Generate a programming file for the target FPGA
    
      modules: Synthesize OR1200 processor, debug interface, UART and Ethernet controllers
      or1200: Synthesize the OR1200 processor
      debug: Synthesize the debug interface
      uart: Synthesize the UART
      eth: Synthesize the Ethernet controller
    
      clean: Delete all superfluous files generated by Xilinx tools
      distclean: Delete all generated files
dev/synthesis.txt · Last modified: 2011/12/10 16:37 by Raul Fajardo