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Development: ModelSim

The simulation script requests the target firmware in hex as its input. The testbench loads the firmware to the SoC memory and runs it. Any data sent by the SoC through UART is printed on the terminal of the running simulator. This allows for feedback of the simulation (firmware/processor working) without the requirement of specifically debugging it.


Simulation and Debugging Module

The simulation under ModelSim requires that you compile a VPI module under “minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/<modelsim_linux_x86|modelsim_win32>”.

  • Linux:
    cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_linux_x86
    cp minsoc/bench/verilog/vpi
  • Windows:
    • in most cases you can simply copy the pre-compiled win32 vpi library jp-io-vpi.dll from minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32 to minsoc/bench/verilog/vpi.
    • alternatively, you can re-compile it with with mingw as follows:
      cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32
      cp jp-io-vpi.dll minsoc/bench/verilog/vpi

Info: You will probably have to edit the Makefiles to input correct pathes for compilation includes. Under Windows, mingw is installed together with ModelSim.

Rip off Debugging Module

If the procedure above does not work, you can still simulate by removing the debugging module from your system.

  1. edit minsoc/prj/src/minsoc_bench.prj
    • comment dbg_comm_vpi.v
    • cd minsoc/prj
    • make
  2. edit minsoc/backend/minsoc_bench_defines.v
    • comment `define VPI_DEBUG
  3. edit minsoc/sim/modelsim/run_sim.<bat|sh>
    • remove the following part: -pli ../../bench/verilog/vpi/jp-io-vpi.<dll|so>


How To

  1. Command to start testbench and select firmware
    • From minsoc/sim/modelsim/
      ./run_sim <your_firmware.hex> (e.g. ./run_sim ../../sw/uart/uart.hex) 

* Notice that you are also able to debug the simulation. To do so, check this.


Windows user can click on the .bat files of the same name instead. However, they have to respect the same order:

  1. prepare_modelsim.bat
  2. compile_design.bat
  3. run_sim.bat
dev/modelsim_simulation.txt · Last modified: 2011/11/28 12:24 by Raul Fajardo