The simulation script requests the target firmware in hex as its input. The testbench loads the firmware to the SoC memory and runs it. Any data sent by the SoC through UART is printed on the terminal of the running simulator. This allows for feedback of the simulation (firmware/processor working) without the requirement of specifically debugging it.
The simulation under ModelSim requires that you compile a VPI module under “minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/<modelsim_linux_x86|modelsim_win32>”.
cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_linux_x86 make cp jp-io-vpi.so minsoc/bench/verilog/vpi
cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/modelsim_win32 make cp jp-io-vpi.dll minsoc/bench/verilog/vpi
Info: You will probably have to edit the Makefiles to input correct pathes for compilation includes. Under Windows, mingw is installed together with ModelSim.
If the procedure above does not work, you can still simulate by removing the debugging module from your system.
./prepare_modelsim.sh ./compile_design.sh ./run_sim <your_firmware.hex> (e.g. ./run_sim ../../sw/uart/uart.hex)
* Notice that you are also able to debug the simulation. To do so, check this.
Windows user can click on the .bat files of the same name instead. However, they have to respect the same order: