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1_0:project_definition

Release 1.0: Project Definition

Simulation and synthesis of Verilog or VHDL code require the definition of a project scope. This is done differently for the different synthesis and simulation tools. This can be a source of errors and design mismatches if for instance the definitions of simulation and synthesis project differ.

To tackle that, MinSoC automatized the creation of projects for different tools. Instead of using a tool project definition, MinSoC uses a custom project definition based on bash arrays for files and directories lists for a module. With defined bash arrays, bash scripts include these arrays and generate the following project descriptions:

  • Simulation (Icarus Verilog and ModelSim)
  • Altera Project for Bitfile Generation
  • Xilinx Project for Bitfile Generation

Using MinSoC's Project

Every RTL module is described in a file under minsoc/prj/src. You can include a module to MinSoC by creating a new file. Alternatively you can update an RTL module's directories or files. If you created a new file, simply add it to the minsoc/prj/Makefile VERILOG_PROJECTS or VHDL_PROJECTS variables. Now, you can re-run make to automatically update the supported tool projects.

Summarizing:

  • Updating a module:
    1. Edit the src/module.prj file. Include files or directories.
    2. Re-run make under minsoc/prj
  • Including a new module:
    1. Create a src/new_module.prj file.
    2. Create two bash variables PROJECT_DIR and PROJECT_SRC containing a list of the module's directories and files respectively. 1)
    3. Edit minsoc/prj/Makefile, include the new created file either to VHDL_PROJECTS or VERILOG_PROJECTS bash variable. 2)
    4. Re-run make under minsoc/prj

Information: If you have already configured your board, you have to re-run the configure script. If you included a new module to your project, the SYN_FILE variable of the script has to be updated to include the newly created project description file for synthesis.

That happens because the synthesis project files have to be patched for their device and family parts before being used in synthesis. This issue has been spotted and is planed to be dealt with after release 1.0. More details here.

MinSoC's Project Explanation

MinSoC Project is defined under the minsoc/prj directory. The prj directory contains the following files and directories:

minsoc/prj/
  altera/
  scripts/
  sim/
  src/
  xilinx/
  Makefile

In the src directory, there is a project file (something.prj) with the description of the corresponding files and directories of the module. This is the example of the minsoc_top.prj:

PROJECT_DIR=(backend rtl/verilog rtl/verilog/minsoc_startup rtl/verilog/or1200/rtl/verilog rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog rtl/verilog/ethmac/rtl/verilog rtl/verilog/uart16550/rtl/verilog)
PROJECT_SRC=(minsoc_defines.v
timescale.v
minsoc_top.v
minsoc_tc_top.v
minsoc_onchip_ram.v
minsoc_onchip_ram_top.v
minsoc_clock_manager.v
altera_pll.v
xilinx_dcm.v
minsoc_xilinx_internal_jtag.v
spi_top.v
spi_defines.v
spi_shift.v
spi_clgen.v
OR1K_startup_generic.v)

No matter if the project is written in Verilog or VHDL, this is always MinSoC's way to describe a project.

The Makefile encloses the collection of projects to be exported to the different tool projects:

VERILOG_PROJECTS = minsoc_bench.prj minsoc_top.prj or1200_top.prj adbg_top.prj jtag_top.prj uart_top.prj ethmac.prj
VHDL_PROJECTS = altera_virtual_jtag.prj
...

It also separates Verilog projects from VHDL projects because some tools have to include Verilog and VHDL projects differently.

Finally, the Makefile has targets calling the scripts under minsoc/scripts to transform the MinSoC's projects into the corresponding tool projects:

altvprj.sh
altvhdprj.sh
simverilog.sh
simvhdl.sh
xilinxprj.sh
xilinxxst.sh
1) Check minsoc_top.prj below as an example of how to define the variables
2) Check Makefile below as an example of the variables
1_0/project_definition.txt · Last modified: 2011/11/28 12:29 by Raul Fajardo