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Release 1.0: Board Configuration

How To

If your board is supported, you find a subdirectory under minsoc/backend with your board name. Go to that subdirectory and run the configuration script:

cd minsoc/backend/my_board

Your system is now configured, you can proceed with the synthesis.

If your board is not supported and it embeds an Altera or Xilinx FPGA, create a board support. This way, simulation and synthesis can be done in MinSoC's standard way.

For boards with FPGAs from other manufacturers, the MinSoC's Makefile system for synthesis will not work. Simulation should work normally, as far as you edit the files but leave them in their current location. For synthesis, proceed to manual synthesis.

Board Support

As long as a board embeds an Altera or Xilinx FPGA, you can create its support to MinSoC in the 3 following steps. Although it is not necessary, I recommend you to read MinSoC's Configuration before proceeding, so you understand what you are doing.

Creating a Board Configuration

Create a subdirectory of backend with the name of your board, minsoc/backend/my_board for example.

cd minsoc/backend
mkdir my_board

Then, copy either the contents of an Altera or Xilinx backend subdirecotories to your subdirectory. For Xilinx, use std, for Altera altera_3c25_board.

cp std/* my_board/

Go to your subdirectory and edit the configuration script.

cd my_board
gedit configure

Updating the configuration script:

  1. edit the BOARD variable to the name of the directory you created.
  2. edit the DEVICE_PART variable to the name of your FPGA part.
  3. edit CONSTRAINT_FILE variable to the constraint file you have created.
  4. edit FAMILIY_PART to the name of your FPGA family, Altera only.

Save and exit.

Extensions: If you have included other modules by creating project files, add them using the SYN_FILES. 1) If your project has extra system specific files, include them to BOARD_FILES.

Proceed now to adapt the system to your board.

Adapting the System to your Board

This section guides you in adapting MinSoC to your custom board. In the linked pages of the text, some files are said to be located under various directories. You have to edit the files under minsoc/backend/my_board instead. The only exception is or1200_defines.v, but you can as well ignore the configuration of this file.

  1. Configure minsoc/backend/my_board/minsoc_defines.v. 2)
    1. Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it. In case your FPGA is neither Altera nor Xilinx, MinSoC's synthesis does not work, use manual synthesis instead.
    2. `define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by 4⋅2MEMORYADRWIDTH bytes, since its data width is 32 bits, the amount in Bytes is 4 times its depth. 3)
    3. Choose a clock division for your global clock related to your design max speed by changing the definition: “`define CLOCK_DIVISOR 5”. 4)
    4. Define your RESET polarity: uncomment “`define POSITIVE_RESET” for an active high reset or “`define NEGATIVE_RESET” for an active low reset and comment the other.
    5. At the bottom you will find the statement
      `ifdef GENERIC_FPGA

      Below this, you need to undefine the FPGA family and FPGA manufacturer. This is used during simulation, when GENERIC_FPGA is defined by the test bench. For instance, if you chose a XILINX_FPGA and SPARTAN3E, you would include

      `undef XILINX_FPGA
      `undef SPARTAN3E
  2. Define user constrains for system pinout. To do so, edit or create minsoc/backend/your_board.ucf file. Here you find some examples of ucf files. More examples are found under minsoc/backend/someboard/someboard.ucf.
    • The constraint file is required to define which FPGA pins are connected to which design ports. You will have to check the user manual for your board. It will tell you which FPGA pins are connected to which board components. Then, change the FPGA pin names inside quotes after <LOC = > for every design port according to the user manual information of your board.

Testing your Board Configuration

Now run the configure script under minsoc/backend/my_board.

cd my_board

Test simulation and synthesis.

  • If the simulation does not work, be sure that you have followed item 1.V. of system adaption.
  • If the design does not fit onto the FPGA, check this link for optimizations.
  • If all went well, your board can be committed to mainstream. Send an email to with subject “board support: my_board” and a compressed file of your my_board directory.

MinSoC's Configuration

System Configuration

All system specific files of MinSoC are found under minsoc/backend. These are:

  • board.h: board information for the enclosed firmwares
  • optional gcc flags when compiling the enclosed firmwares
  • minsoc_bench_defines.v: configuration of testbench
  • minsoc_defines.v: configuration of system
  • orp.ld: memory configuration for the firmware compiled binaries
  • your_board.ucf: synthesis constraints, FPGA pinout

You can tweak configurations by editing these files.

Automatic Configuration

Under each subdirectory of minsoc/backend, there is a configure script which does the following:

  1. copy the system specific files to backend
  2. re-generate project files for simulation and synthesis 5)
  3. copy synthesis project files from minsoc/prj/altera|xilinx to minsoc/syn/buildSupport
  4. patch synthesis project files to include the device part code, xc3sd1800a-4-fg676 for example.
  5. copy xilinx or altera Makefile from minsoc/syn/xilinx|altera to minsoc/syn
  6. patch Makefile to add the name of the constraint file defining the FPGA pinout, spartan3a_dsp_kit.ucf for example.

This way, simulation and synthesis are ready.

If your board is not currently supported in MinSoC, this link explains how to create a board support for it.

Using MinSoC for multiple projects simultaneously

In some circunstances, you may want to develop several MinSoC based projects with different modules and, maybe, using different FPGA's vendors.

For this situation you have two options:

  1. Using several copies (one for each project) of the MinSoC's directory tree. You need this because for each project you will need differents minsoc_defines.v and minsoc_top.v files.
  2. Using a directory for each project with your own minsoc_defines.v and minsoc_top files and with a customized Makefile file for the synthesis.

The first option means that you will have a lot of redundant directories into your system and for each update in MinSoC you will need to update all your repos. For the second option, you need to make your directory, copy (by hand) your minsoc_defines.v and minsoc_top.v files and write your own Makefile (among other things) for each project. This breaks the usability and facility of the board-based configuration scripts described above.

So, for the case you need to deploy several instances of MinSoc, there is a script called into minsoc/utils/setup/ directory.

When you launch this script from your current directory, it ask you for some params like device vendor and part and generates all the necesary files for sinthesis.

Actually, this script only has support for Altera devices (althought it ask for Xilinx ones too). The usage is in this way:

  1. First of all, you need to export the MINSOC_DIR system variable. You can setup into your .bashrc file by adding this:
export MINSOC_DIR=path_to_your_minsoc_tree
  1. will ask you for some files. If you are deploying a project for Altera devices, it will ask for three files:
    1. A file containing a list of paths (one per line) where find any verilog file to include in your final project.
    2. A file containing a list of paths (one per line) where find any VHDL file to include in your final project.
    3. An User Constraint File containing constraints (for example, pin configuration) for your final project.
  2. Once you have all your files (only UCF file is mandatory), you can launch script. At first, it will ask you for the device you are going to use, the device vendor and the device family.
  3. Later, it will ask you for the files described before. After enter all your files, you will see a report of your configuration.
  4. Finally, by pressing Enter, will start deploying and patching all the files you need for your project. It will add your modules files (VHDL or Verilog) and apply the constraints of your UCF file generating a project file and a Makefile for your platform.
  5. Once you have all your files in your directory, you need to edit your minsoc_defines.v and minsoc_top.v files for connect your modules.
  6. And that's done!!! You only have to type make and your project will start building. limitations

By now, the script is in an early stage and is not yet completed. Althought it can deploy a complete project based on Altera's devices, it has several limitations:

  1. No support for Xilinx devices.
  2. Althought you specify your device part, family and vendor, the script only uses this information for the project file, and you need to edit your minsoc_defines.v file in order to setup your device by hand.
  3. By now, you need to edit the script by hand for add new parts.
  4. No deployment of firmware directory (you need to create and edit by hand a Makefile for link with the base drivers).
1) , 5) Please refer to project_definition for further details
2) This link shows recommended values for different devices
3) This is not allowed to be less than 12, 11 is the memory block address width. If you change it from 13, check FAQ: How to adapt the firmware to my implementation?.
4) If your resulting clock is not 25MHz, check FAQ: How to adapt the firmware to my implementation?.
1_0/board_configuration.txt · Last modified: 2013/02/10 00:40 by Javier Almansa