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0_9:synthesis_examples

Release 0.9: Synthesis Examples

Note: different constraint files for different boards → inside of backend directory

Altera Devices

  1. minsoc/rtl/verilog/minsoc_defines.v
    uncomment `define ALTERA_FPGA
    comment `define XILINX_FPGA
    uncomment your device on FPGA family
    comment all other definitions of Altera FPGA family
    select your memory amount "`define MEMORY_ADR_WIDTH 13"
    choose a clock division for your global clock related to your design max speed by changing the definition: "`define CLOCK_DIVISOR 5". Since you have an Altera device please use only even numbers for the division, odd numbers are going to be rounded down.
    Define your RESET polarity uncommenting "`define POSITIVE_RESET" or "`define NEGATIVE_RESET" and commenting the other.
  2. minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v
    uncomment `define OR1200_ALTERA_LPM
    include `define OR1200_ALTERA_LPM_XXX

Spartan 3A DSP 1800

  1. minsoc/rtl/verilog/minsoc_defines.v
    uncomment `define XILINX_FPGA
    comment `define ALTERA_FPGA
    uncomment `define SPARTAN3A
    comment all other definitions of Xilinx FPGA family
    define MEMORY_ADR_WIDTH as 15: `define MEMORY_ADR_WIDTH   15 (in case it is not already this value)
    define CLOCK_DIVISOR as 5: `define CLOCK_DIVISOR 5 (in case it is not already this value)
    uncomment `define POSITIVE_RESET
    comment `define NEGATIVE_RESET
  2. minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v (optional, reduce logic use)
    uncomment `define OR1200_XILINX_RAMB16

Spartan 3E Starter Kit no Ethernet

  1. minsoc/rtl/verilog/minsoc_defines.v
    uncomment `define XILINX_FPGA
    comment `define ALTERA_FPGA
    uncomment `define SPARTAN3E
    comment all other definitions of Xilinx FPGA family
    define MEMORY_ADR_WIDTH as 13: `define MEMORY_ADR_WIDTH   13 (in case it is not already this value)
    define CLOCK_DIVISOR as 2: `define CLOCK_DIVISOR 2 (in case it is not already this value)
    uncomment `define POSITIVE_RESET
    comment `define NEGATIVE_RESET
    comment `define ETHERNET
  2. minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v
    uncomment `define OR1200_XILINX_RAMB16
    uncomment `define OR1200_NO_DC
    uncomment `define OR1200_NO_IC
    uncomment `define OR1200_NO_DMMU
    uncomment `define OR1200_NO_IMMU

Spartan 3E Starter Kit with Ethernet

  1. Synthesis properties:
    • Optimization Goal: Area
    • Optimization Effort: High
  2. minsoc/rtl/verilog/minsoc_defines.v
    uncomment `define XILINX_FPGA
    comment `define ALTERA_FPGA
    uncomment `define SPARTAN3E
    comment all other definitions of Xilinx FPGA family
    define MEMORY_ADR_WIDTH as 12: `define MEMORY_ADR_WIDTH   12 (in case it is not already this value)
    define CLOCK_DIVISOR as 5: `define CLOCK_DIVISOR 5 (in case it is not already this value)
    uncomment `define POSITIVE_RESET
    comment `define NEGATIVE_RESET
    uncomment `define ETHERNET
    comment `define UART
    • This last is not necessary, though you will get 99% device usage if not commenting, 89% otherwise.
  3. minsoc/rtl/verilog/or1200/rtl/verilog/or1200_defines.v
    uncomment `define OR1200_XILINX_RAMB16
    uncomment `define OR1200_NO_DC
    uncomment `define OR1200_NO_IC
    uncomment `define OR1200_NO_DMMU
    uncomment `define OR1200_NO_IMMU
    comment `define OR1200_MULT_IMPLEMENTED
    comment `define OR1200_MAC_IMPLEMENTED
    comment `define OR1200_PM_IMPLEMENTED
    comment `define OR1200_CFGR_IMPLEMENTED
  4. minsoc/rtl/verilog/ethmac/rtl/verilog/eth_defines.v
    uncomment `define ETH_FIFO_XILINX
    uncomment `define ETH_XILINX_RAMB4
  • Collateral effects:
    1. from sw/support/Makefile.inc line 7:
      GCC_OPT=-mhard-mul -g to GCC_OPT=-msoft-mul -g
    2. change sw/support/orp.ld:
      1. ram: LENGTH = from 0x00006E00 to 0x00002E00
      2. This is not much memory, I recommend the inclusion of the wb_ddr project to minsoc to use your DDR SRAM memory
    3. change sw/support/board.h
      1. IN_CLK to 10000000 ((10MHz) this will make the simulation have problems with the uart output but will work on implementation)
      2. STACK_SIZE to 0x00180
      3. UART_BAUD_RATE to 9600 (baudrate 115200 leads to a high baudrate skew due to a truncation. PC cannot recognize the output)
    4. reduce sw/eth.c: deprecated, valid until version 35, you can downgrade to proceed as this. Run “svn update -r 35” under /minsoc to do so.
      remove lines 230-231
      remove lines 215-220
      remove line 206
      remove line 202
      change uart_print_long to uart_print_short, line 162
      change lines 98 and 99 to char tx_data[64] and char rx_data[64]
      remove lines 53-70 void uart_print_long(unsigned int ul) {}
      remove lines 31-42 void uart_interrupt(){}
  • Further area optimization possibilities: (not necessary, DON'T DO)
    • Turn off: pic, tick timer or debug unit
0_9/synthesis_examples.txt · Last modified: 2011/10/25 12:30 by Raul Fajardo