Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it in case you have a Xilinx FPGA, for Altera comment all out.
`define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by 4⋅2MEMORYADRWIDTH bytes, since its data width is 32 bits, the amount in Bytes is 4 times its depth. 2)
Choose a clock division for your global clock related to your design max speed by changing the definition: “`define CLOCK_DIVISOR 5”. 3)
Define your RESET polarity: uncomment “`define POSITIVE_RESET” for an active high reset or “`define NEGATIVE_RESET” for an active low reset and comment the other.
Define user constrains for system pinout. To do so, edit or create minsoc/backend/yourboard.ucf file. Here you find some examples of ucf files.
The constraint file is required to define which FPGA pins are connected to which design ports. Open an example from minsoc/backend/someboard.ucf. If your board is not present, you will have to check the user manual for your board. It will tell you which FPGA pins are connected to which board components. Then, change the FPGA pin names inside quotes after <LOC = > for every design port according to the user manual information of your board.
Create project in project manager (ISE, Quartus), include all Verilog files under “minsoc/rtl/verilog” and subdirectories.
Include the user constraint for system pinout (created on step 3) to your project on the project manager.