User Tools

Site Tools


0_9:synthesis

Release 0.9: Synthesis

How To

  1. Configure minsoc/rtl/verilog/minsoc_defines.v. 1)
    1. Select your FPGA device by uncommenting its manufacturer and commenting all other manufacturers. Select then your FPGA model by uncommenting it in case you have a Xilinx FPGA, for Altera comment all out.
    2. `define MEMORY_ADR_WIDTH 13 defines the amount of memory you get. The depth is defined by 4⋅2MEMORYADRWIDTH bytes, since its data width is 32 bits, the amount in Bytes is 4 times its depth. 2)
    3. Choose a clock division for your global clock related to your design max speed by changing the definition: “`define CLOCK_DIVISOR 5”. 3)
    4. Define your RESET polarity: uncomment “`define POSITIVE_RESET” for an active high reset or “`define NEGATIVE_RESET” for an active low reset and comment the other.
  2. Configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v.
    • comment out, “`define DBG_JSP_SUPPORTED”.
  3. Define user constrains for system pinout. To do so, edit or create minsoc/backend/yourboard.ucf file. Here you find some examples of ucf files.
    • The constraint file is required to define which FPGA pins are connected to which design ports. Open an example from minsoc/backend/someboard.ucf. If your board is not present, you will have to check the user manual for your board. It will tell you which FPGA pins are connected to which board components. Then, change the FPGA pin names inside quotes after <LOC = > for every design port according to the user manual information of your board.
  4. Create project in project manager (ISE, Quartus), include all Verilog files under “minsoc/rtl/verilog” and subdirectories.
  5. Include the user constraint for system pinout (created on step 3) to your project on the project manager.
  6. Synthesize, P&R and upload bitfile. 4)

Here you find some configuration examples for the SoC synthesis of known boards and FPGA models.

Only after the bitfile has been successfully uploaded, OpenRISC firmware can be uploaded and debugged, how to.

1) This link shows recommended values for different devices
2) This is not allowed to be less than 12, 11 is the memory block address width. If you change it from 13, check FAQ: How to adapt the firmware to my implementation?.
3) If you have an Altera device please use only even numbers for the division, odd numbers are going to be rounded down. If your resulting clock is not 25MHz, check FAQ: How to adapt the firmware to my implementation?.
4) If your device is full check this link for optimizations.
0_9/synthesis.txt · Last modified: 2011/12/10 16:39 by Raul Fajardo