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0_9:simulation

Release 0.9: Simulation

The simulation script requests the target firmware in hex as its input. The testbench loads the firmware to the SoC memory and runs it. Any data sent by the SoC through UART is printed on the terminal of the running simulator. This allows for feedback of the simulation (firmware/processor working) without the requirement of specifically debugging it.

  1. Configure minsoc/rtl/verilog/adv_debug_sys/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
    • Comment out, “`define DBG_JSP_SUPPORTED”
  2. Command to start testbench and select firmware
    • From minsoc/sim/run/
      ./generate_bench
      ./run_bench <your_firmware.hex> (e.g. ./run_bench ../../sw/uart/uart-nocache-twobyte-sizefirst.hex) 

* Notice that you are also able to debug the simulation. To do so, check this.

0_9/simulation.txt · Last modified: 2011/10/25 12:30 by Raul Fajardo