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0_9:installation

Release 0.9: MinSoC Installation

For Windows installation check this first. Linux users can follow this guide directly. If you run Linux and cannot install the original cable drivers to upload bitfiles, try this.

Install Icarus Verilog

You will need at least version 0.9.1 (ftp://ftp.icarus.com/pub/eda/verilog/v0.9/).

If you are using a Debian/Ubuntu Linux the package name is “iverilog”.

Setup MinSoC Environment

  1. Download minsoc and required external IP cores:
    svn co http://opencores.org/ocsvn/minsoc/minsoc/tags/release-0.9/ minsoc
    cd minsoc/rtl/verilog
    svn co http://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk adv_debug_sys
    svn co http://opencores.org/ocsvn/ethmac/ethmac/tags/rel_27 ethmac
    svn co http://opencores.org/ocsvn/openrisc/openrisc/trunk/or1200 or1200
    svn co http://opencores.org/ocsvn/uart16550/uart16550/trunk uart16550

Install GNU toolchain and adv_jtag_bridge

  1. Follow: http://www.opencores.org/openrisc,gnu_toolchain (to install binutils, gcc, gdb)
  2. To debug and load the firmware you have to use the new advanced_debug_system. This project is included in the minsoc files inside of minsoc/rtl/verilog/adv_debug_sys. There you can find the software in Software and the documentation, which shall help you to go under Doc.
    Change the Makefile in minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge and compile the software using make.
    cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge
    sed 's/INCLUDE_JSP_SERVER=true/INCLUDE_JSP_SERVER=false/' Makefile > TMPFILE && mv TMPFILE Makefile
    make
    sudo make install
  3. If you have a Xilinx FPGA: copy the description file of your FPGA to your home directory (e.g. “cp /opt/Xilinx/10.1/ISE/spartan3e/data/xc3s500e_fg320.bsd ~/”).
  4. With the adv_jtag_bridge you can also debug your simulation. To do so, the simulation has to include a vpi module. This has to be compiled by your system. The sources are found under “minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus”.
    cd minsoc/rtl/verilog/adv_debug_sys/Software/adv_jtag_bridge/sim_lib/icarus
    make
    cp jp-io-vpi.vpi minsoc/bench/verilog/vpi
  5. Install a patched version of GDB 6.8 as described here, otherwise you will have issues setting the program counter:
    • Info: FAQ, “GDB reports “Value being assigned to is no longer active.”, what happened?”

Compile Software

Inside of sw/utils:

make

Inside of sw/support:

make

Inside of sw/drivers:

make

Inside of the target software (e.g. sw/uart)

make
0_9/installation.txt · Last modified: 2011/10/25 13:14 by Raul Fajardo